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<div class="header">
  <div class="headertitle"><div class="title">SWPMI_TypeDef Struct Reference<div class="ingroups"><a class="el" href="group___c_m_s_i_s___device.html">CMSIS_Device</a> &raquo; <a class="el" href="group__stm32h723xx.html">Stm32h723xx</a> &raquo; <a class="el" href="group___peripheral__registers__structures.html">Peripheral_registers_structures</a></div></div></div>
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<p>Single Wire Protocol Master Interface SPWMI.  
 <a href="#details">More...</a></p>

<p><code>#include &lt;<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a>&gt;</code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-pub-attribs" class="groupheader"><a id="pub-attribs" name="pub-attribs"></a>
Public Attributes</h2></td></tr>
<tr class="memitem:aecc2dc56573d57f5f476c380892ea2e2" id="r_aecc2dc56573d57f5f476c380892ea2e2"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aecc2dc56573d57f5f476c380892ea2e2">CR</a></td></tr>
<tr class="memitem:a24dca3d3fef0dbae21b72d6c9f98ac82" id="r_a24dca3d3fef0dbae21b72d6c9f98ac82"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a24dca3d3fef0dbae21b72d6c9f98ac82">BRR</a></td></tr>
<tr class="memitem:a96cbc61176016e59e5f221a6f5883420" id="r_a96cbc61176016e59e5f221a6f5883420"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a96cbc61176016e59e5f221a6f5883420">RESERVED1</a></td></tr>
<tr class="memitem:a74f559fbb6982164f17b971ddfff705c" id="r_a74f559fbb6982164f17b971ddfff705c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a74f559fbb6982164f17b971ddfff705c">ISR</a></td></tr>
<tr class="memitem:af29489661b1cc547d5a61c7798a89f69" id="r_af29489661b1cc547d5a61c7798a89f69"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#af29489661b1cc547d5a61c7798a89f69">ICR</a></td></tr>
<tr class="memitem:acf541fac1b5a52320d3d4306f5e81dd8" id="r_acf541fac1b5a52320d3d4306f5e81dd8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#acf541fac1b5a52320d3d4306f5e81dd8">IER</a></td></tr>
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<tr class="memitem:a717971a9ac0ea8710ad884efd6eb8b0b" id="r_a717971a9ac0ea8710ad884efd6eb8b0b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a717971a9ac0ea8710ad884efd6eb8b0b">TDR</a></td></tr>
<tr class="memitem:a3084e031419c7432cb0b79ac256bc308" id="r_a3084e031419c7432cb0b79ac256bc308"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#a3084e031419c7432cb0b79ac256bc308">RDR</a></td></tr>
<tr class="memitem:aa70799e3ee75fd0a748b46139ee69d4f" id="r_aa70799e3ee75fd0a748b46139ee69d4f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#aa70799e3ee75fd0a748b46139ee69d4f">OR</a></td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Single Wire Protocol Master Interface SPWMI. </p>
</div><a name="doc-variable-members" id="doc-variable-members"></a><h2 id="header-doc-variable-members" class="groupheader">Member Data Documentation</h2>
<a id="a24dca3d3fef0dbae21b72d6c9f98ac82" name="a24dca3d3fef0dbae21b72d6c9f98ac82"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a24dca3d3fef0dbae21b72d6c9f98ac82">&#9670;&#160;</a></span>BRR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWPMI_TypeDef::BRR</td>
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<p>SWPMI bitrate register, Address offset: 0x04 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aecc2dc56573d57f5f476c380892ea2e2">&#9670;&#160;</a></span>CR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWPMI_TypeDef::CR</td>
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<p>SWPMI Configuration/Control register, Address offset: 0x00 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#af29489661b1cc547d5a61c7798a89f69">&#9670;&#160;</a></span>ICR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWPMI_TypeDef::ICR</td>
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<p>SWPMI Interrupt Flag Clear register, Address offset: 0x10 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#acf541fac1b5a52320d3d4306f5e81dd8">&#9670;&#160;</a></span>IER</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWPMI_TypeDef::IER</td>
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<p>SWPMI Interrupt Enable register, Address offset: 0x14 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a74f559fbb6982164f17b971ddfff705c">&#9670;&#160;</a></span>ISR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWPMI_TypeDef::ISR</td>
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<p>SWPMI Interrupt and Status register, Address offset: 0x0C </p>

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<h2 class="memtitle"><span class="permalink"><a href="#aa70799e3ee75fd0a748b46139ee69d4f">&#9670;&#160;</a></span>OR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWPMI_TypeDef::OR</td>
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<p>SWPMI Option register, Address offset: 0x24 </p>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWPMI_TypeDef::RDR</td>
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<p>SWPMI Receive data register, Address offset: 0x20 </p>

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          <td class="memname">uint32_t SWPMI_TypeDef::RESERVED1</td>
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<p>Reserved, 0x08 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a16d5b62f16b36dda2c3c37cdb34dc335">&#9670;&#160;</a></span>RFL</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWPMI_TypeDef::RFL</td>
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<p>SWPMI Receive Frame Length register, Address offset: 0x18 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#a717971a9ac0ea8710ad884efd6eb8b0b">&#9670;&#160;</a></span>TDR</h2>

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          <td class="memname"><a class="el" href="core__armv81mml_8h.html#aec43007d9998a0a0e01faede4133d6be">__IO</a> uint32_t SWPMI_TypeDef::TDR</td>
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<p>SWPMI Transmit data register, Address offset: 0x1C </p>

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<hr/>The documentation for this struct was generated from the following file:<ul>
<li>C:/Users/ASUS/Desktop/dm-ctrlH7-balance-9025test/Drivers/CMSIS/Device/ST/STM32H7xx/Include/<a class="el" href="stm32h723xx_8h_source.html">stm32h723xx.h</a></li>
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